The design rules for minimum line width (minimum feature size) of semiconductor integrated circuits are presently progressing to values below one micrometer. Accordingly, technologies featuring self-aligned metal silicide contact electrodes, or other self-aligned metallization contact electrodes, serving as the high-current-carrying (controlled) transistor terminals (source and drain terminals in unipolar transistors, emitter and collector in bipolar transistors) become increasingly attractive commercially, primarily by virtue of the reduced series resistance of the transistors. The self-alignment of the high-current-carrying contact electrodes is in general in addition to self-alignment of control electrodes, i.e., the low-current-carrying transistor terminals (gate terminals in unipolar transistors, base terminals in bipolar transistors).
An important self-aligned electrode contact technology, the self-aligned silicide MOS technology, illustrates quite clearly the problems arising from fabricating test circuits for measuring specific contact resistivity, r.sub.c (measured in units of ohm-cm.sup.2, for example). For the sake of definiteness, first the self-aligned silicide MOS technology will be discussed in detail, but it should be understood that similar problems arise in other self-aligned electrode contact technologies, such as self-aligned metallization by means of selective tungsten metal deposition (without forming silicide) using low pressure chemical vapor deposition techniques--as taught, for example, in U.S. Pat. No. 4,517,225, issued to E. K. Broadbent on May 14, 1985, entitled "Methods for Manufacturing an Electrical Interconnection by Selective Tungsten Deposition"--which can be used for making self-aligned metallization electrode contacts for MOS transistors, for MESFETs (metal gate field effect transistors), or for bipolar transistors. In the self-aligned silicide MOS technology, each of the MOS transistor source-drain contact electrodes is composed of a metal silicide layer in physical contact, and hence in electrical contact, with a diffused source or drain region at a top major surface of an underlying silicon wafer. Moreover, these metal silicide source-drain electrodes are formed by deposition of the metal, followed by sintering of the deposited metal to form metal silicide wherever silicon (including exposed silicon of a silicon gate, if any) underlies the metal at a time when the sidewalls of the gate electrode are coated with a protective insulating layer, typically a sidewall oxide layer, whereby each of the resulting metal silicide source-drain contact electrodes automatically has an edge which is laterally displaced from an edge of the nearest gate electrode only by the thickness of the sidewall oxide layer. Thus each metal silicide source-drain electrode is self-aligned; that is, no extra lithographic step was required thus to align an edge of each source-drain electrode with an edge of the gate electrode: the alignment was automatically determined by the thickness of the sidewall oxide. Furthermore, since the thickness of the sidewall oxide is small relative to the minimum feature size, the lateral displacement of the silicide electrode edge relative to the gate electrode edge is relatively small.
Also, in self-aligned silicide MOS technology, significant impurities, donors or acceptors, or both--to form the MOS transistor source-drain diffused regions located in surface portions of the silicon wafer underlying th metal silicide source-drain electrodes--are introduced into and diffused in the silicon wafer either before or after the deposition of the metal. In either event, the eges of the source-drain diffused regions are thus themselves self-aligned with respect to the corresponding edges of the gate electrode, but are laterally displaced therefrom at slightly different distances from those of the source-drain electrodes, depending upon the specific source-drain diffusion conditions and parameters thereof.
Now, in accordance with the ordinary silicon integrated circuit (IC) fabrication procedures, including those used in self-aligned silicide technology, the circuits corresponding to a plurality of IC chips are all simultaneously fabricated on a single silicon wafer. When fabrication of all the integrated circuits on the silicon wafer has been completed, the wafer is scribed and cut up into the plurality of IC chips. Similar procedures can be employed in other MOS self-aligned metallization technologies, as well as in MESFETs and in bipolar transistors made in silicon or in gallium arsenide semiconductor.
Many are the causes and types of failure mechanisms in IC chips, and failures in self-aligned silicide technology, as well as in other self-aligned metallization technologies, are no exception. Some of these failure mechanisms--both in self-aligned-silicide technology and in other, non-self-aligned silicide technologies--fortunately can be detected at a relatively early stage of fabrication, so that upon such early detection of a failure mechanism, fabrication can be terminated before all IC fabrication steps have been completed or at least before the wafer is scribed and cut into individual chips, depending upon when the failure is detected. Thus economic costs of failures can be reduced. One technique for achieving this early detection of failures is the utilization of test circuits integrated in non-IC-chip areas (test circuit areas) of the wafer--i.e., areas located between future chips, areas located at the periphery of the wafer, as well as any other areas of the wafer where no workable chips are to be fabricated. Specifically, these non-IC-chip areas are utilized for the fabrication of the test circuits by means of, for example, self-aligned silicide processing which is performed simultaneously with the same self-aligned silicide processing of the chip circuits integrated in IC chip areas, viz., areas where the ultimately desired IC chips are to be located on the wafer. By virtue of this simultaneous fabrication of chip circuits and test circuits, the semiconductor processing parameters of test circuits and chips circuits are automatically virtually the same (except for negligible processing variations across the surface of the wafer). Hence, the device parameters--such as specific contact resistivity r.sub.c of electrode contacts to diffused regions of the semiconductor wafer and sheet (lateral) resistivity r.sub.s of the diffused regions--are also automatically virtually the same for the test circuits as for the chip circuits. Indirect testing of the chip circuits by means of direct testing of the test circuits thus becomes feasible and meaningful at an early stage of manufacture. The same tests can be deferred, however, until the entire manufacturing process is completed, especially in those cases where failures are expected at late stages of manufacture.
An important failure mechanism in integrated circuits, both in self-aligned and in non-self-aligned metallization technologies, is manifested by unduly high specific contact resistivity r.sub.c of electrodes to underlying diffused regions.
A desirably compact test circuit 1000 (FIG. 1) in the prior art for measuring this specific contact resistivity in non-self-aligned metallization technology is taught, for example, in "Determining Specific Contact Resistivity From Contact End Measurements" by J. G. J. Chern et al, published in IEEE Electron Device Letters, volo EDL-5, pp. 178-180 (1984).
In the test circuit 1000, illustratively for n-channel MOS transistors, a p-type crystal silicon semiconductor wafer 10 has an n.sup.+ type diffused region 11 located at a top major surface 12 of the wafer 10 where each of three mutually spaced-apart contact electrodes 13, 14, 15 make contact with the top exposed surface of the n.sup.+ diffused region 11 at mutually spaced-apart areas. The middle contact electrode 14 intervenes between the other two electrodes 13 and 15. These contact electrodes 13, 14, and 15--typically polycrystalline silicon or Ti:W alloy--serve as barrier layers for overlying aluminum metallization layers 13.5, 14.5, and 15.5 respectively. A field oxide layer 22 and a phosphorus-glass layer 23 complete the test circuit 1000.
During operation, a current source 20 is connected to deliver current I to the electrode 13 while the electrode 14 (in the middle) is grounded and a voltage detector is connected across electrodes 14 and 15. The resulting nonuniform electrical current distribution in the diffused region 11 is indicated in FIG. 1 by a set of broken line arrows representing the current direction and density. Because of the relatively high electrical conductivity of the electrodes 13, 14, and 15, the potential difference between opposite edges of each electrode is negligible. In response to the current I, a voltage V.sub.e is developed between electrodes 14 and 15. This voltage V.sub.e is known to be a measure of the sheet resistance per square r.sub.s of the diffused region 11 and of the specific contact resistivity r.sub.c between the middle electrode 14 and the diffused region 11: EQU V.sub.e =I(r.sub.s r.sub.c).sup.1/2 /W sin h [d(r.sub.s /r.sub.c).sup.1/2 ](1)
where W is the width (perpendicular to the plane of the paper) of the contact of the electrode 14 to the diffused region 11, and d is the length of such contact. See, for example, the above-mentioned paper by J. G. J. Chern et al, at p. 178, col. 2, paragraph 1. By fabricating in the wafer 10 two (or more) such test circuits 1000 with mutually different values of electrode length d, but with the same values of all other parameters, the specific contact resistivity r.sub.c can be calculated by measuring the resulting voltages V.sub.e for the different test circuits and by iteratively applying eq (1) to the two (or more) such circuits 1000 and solving for the two unknown r.sub.s and r.sub.c.
It is also known in prior art that eq. 1 can be simplified by using an L-shaped layout of the diffused region 11, as shown in a paper entitled "Analysis and Scaling of Kelvin Resistors for Extraction of Specific Contact Resistivity" authored by W. M. Loh et al, published in IEEE Electron Device Letters, vol. EDL-6, pp. 105-108 (1985). In the case of the L-shaped layout, it was shown that the specific contact resistivity r.sub.c is given simply by EQU r.sub.c =V.sub.s Wd/I (2)
where V.sub.s is the voltage measured by the voltage measuring device 21. Thus, but a single measurement of voltage enables determination of the specific contact resistivity r.sub.c (but not the sheet resitance r.sub.s).
In the self-aligned silicide MOS process described above, it is likewise desired to measure the specific contact resistivity r.sub.c of the metal silicide source-drain electrodes to the underlying wafer, as well as perhaps the sheet resistance r.sub.s. However, it is not possible to fabricate the circuit 1000 with the three self-aligned silicide electrodes contacting the diffused region 11 of the underlying silicon wafer 10 simultaneously and compatibly with fabrication of the chip circuits (i.e., with no extra lithography steps, which can change the contact resistance), because in the self-aligned silicide process for making, say, n-channel transistors, there is a single metal silicide source-drain electrode directly overlying each diffused n.sup.+ region of the wafer 10. In other words, in any self-aligned metal silicide technology each diffused n.sup.+ region is completely covered by one continuous layer of metal silicide having a relatively high conductivity as compared with that of the diffused region. Thus the current flowing between contacts 13 and 14 would tend to be confined within the metal silicide layer with very little current flowing from the metal silicide layer into the diffused region--where r.sub.s is to be measured--via the interface between the metal silicide layer and the diffused region where the specific contact resistivity r.sub.c is to be measured. Only by means of an added lithography step could the continuity of the self-aligned metal silicide layer be broken in order to force the current from the silicide layer into the n.sup.+ diffused region in order to measure r.sub.c and r.sub.s properly. Such added lithography, however, would change the processing sequence in the test circuits so that the properties of the silicide-silicon interface, and hence the value of r.sub.c in the test circuit, would no longer be necessarily the same as those of the integrated circuits being measured by the test circuit. Thus the measurement of r.sub.c by the test circuit would no longer be meaningful.
Similar problems associated with an added lithography step required for test circuits arise in any other self-aligned metallization contact electrode technology.